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реферат на тему: Physical Methods of Speed-Independent Module Design

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to CL output validity. A high potential output signal corresponds to CL output invalidity. So, OVD generates OV signal in negative logic manner. The transfer characteristics of CVC is determined by a system of three equations:

where I is an input current of CVC, V is a voltage drop on the CVC circuit, Ir is a current flowing through the resistor R1, Id is a current passing through the diode D1, I0 is a leakage current of the diode, rb is a bulk resistance of the diode. Here stands for kT/q where k is Boltzmann's constant, T is absolute temperature, q is charge of an electron. Equations (1)-(3) determine the functional connection F between input current I and voltage drop V: . Graphic solution of the system is shown in Fig.10.

CVC parameters to be calculated are R1 and rb. Initial data for calculating R1 are the threshold voltage drop Vth and corresponding threshold input current Ith . Value Ith is determined by minimal current consumed by CMOS CL in transient state. Initial data for calculating rb are maximal voltage drop Vmax and corresponding maximal input current Imax. Value Imax is determined by the maximal number of gates in CL switching simultaneously and their load capacitances. The comparator chosen is the CMOS ECL receiver proposed by Chappell et al.[11]. The circuit includes a single differential amplifier stage with built-in compensation for parameter variations, followed by a CMOS inverter. The comparator has 100-mV worst-case sensitivity in 1-m technology. Detailed static and dynamic analysis of the comparator circuit was given in [11]. The comparator compares input voltage signal Vin with reference voltage Vref. If Vin Vref, the comparator output signal equals to logical "one" which means that the outputs are invalid. As it follows from the OVD circuit configuration,

where Vdd is a voltage of power supply. Equations (4) and (5) allow us to calculate the threshold voltage drop V of the CVC circuit: since , so If 0750mV, the diode D1 is in active mode and while rb <
The turn-on ton and turn-off toff delays of the OVD circuit depend on the OVD itself and the CMOS CL as well. (Switching the OVD output from low to high voltage is called "turning-on" and reverse switching is called "turning-off".) Consider a piece of CMOS CL and its interaction with OVD circuit (Fig.11). The piece is an SPP including N logic gates. Each gate is shown symbolically as a connection of PMOS and NMOS networks. All the capacitances affecting ton and toff can be brought down to three components: (i) CLi is the
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load capacitance of the i-th gate; (ii) Cpsi is the power supply bus capacitance associated with the i-th gate; (iii) Cin is the input capacitance of the OVD circuit.

Let pi is a probability of the i-th gate being in the state of high output potential. In this state the capacitance CLi is connected with power supply bus through the low channel resistance of turned-on transistors in PMOS network of the i-th gate. Then equivalent capacitance Ceq connected to the OVD circuit input equals

(7) where N is a number of gates in the considered SPP. Here the resistance of conducting PMOS network is assumed to be negligible. Equation (7) is also true for CL including several SPPs. In that case summing must be carried out for all the gates belonging to CL. Simulation shows that ton and toff are proportional to the OVD time constant =R1Ceq. It was also obtained that when N>20, the component under the sign of summation in Equation (7) can be much larger than the component Cin. Due to voltage drop V the effective power supply voltage is reduced and CL performance is decreased by about 35 percent [7]. In order to make SIM operating faster special attention must be paid to reducing the capacitance introduced by CL.

4.3 Speed-independent address bus

The simplest case of CL is a scheme degenerated into a set of wires called a multi-bit bus. Let us develop the OVD circuit for such a CL. Multi-bit bus consists of several lines. Each line can be considered as a medium for signal propagating from one end of the chip to another. Delay of signal propagation through a line depends on several factors: (a) output impedance and symmetry of driver circuit; (b) initial state of the line: if driver is symmetrical, line switching from high to low voltage lasts shorter than reverse switching; (c) electrical properties of the line as a signal propagation medium (resistance of conducting layer and capacitances between the line and other wires next to it); (d) length of the line; (e) input impedance and sensitivity of receiving circuit. Since different lines of the bus operate in different conditions (a)-(e), signal propagation delays are different, too. From the standpoint of environment the bus behaves like any other more complicated CL. Asynchronous RAM designers use a bus transition detector since 1980s [13-15]. Such a detector is usually based on double-rail address coding and two series connected transistors for each address bit [15]. One of the transistors receives the true address signal and the other receives the complementary address signal of the particular address bit. For any steady state condition one of the transistors will be turned on and one will be turned off. There will be a finite rise and fall time during a transition of the address bit. There is a short time during which both transistors are conducting. The establishment of the conductive path provides the detection of the address transition. In the first asynchronous RAMs the output signal of the transition detector is used for bit line precharging and for enabling/disabling sense amplifiers and peripheral circuitry. Self-timed RAM announced in 1983 [14] used transition detectors not for address transition only but also for detecting read/write completion and address/bit line precharge completion as well. The CMOS transition detector was invented in 1986 [15]. This circuit is also based on double-rail coding and uses a pair of series-connected

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