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Не нашли нужную работу? Закажи реферат, курсовую, диплом на заказ реферат на тему: Physical Methods of Speed-Independent Module DesignNMOS transistors (Fig.12). The scheme for n-bit bus control contains n line transition detectors (LTDs) and n AND-gates. Outputs of AND-gates are united in node M forming wired OR. The output inverter serves as a pulse shaper. Capacitors C1 and C2 are intended to prolong rise time of the LTD output signal (true and complementary). This is necessary for reliable detection. 4.4 Speed-independent adder The circuit we use in this Section as a CL was a touch-stone for many speed-independent circuit designers for about four decades. We mean a ripple carry adder (RCA) which is actually a chain of one-bit full adders (Fig.14). Each full adder calculates two Boolean functions: sum si=aibici and output carry ci+1=aibi+bici+aici where ai, bi are summands, ci is input carry and stands for XOR operation. In 1955 Gilchrist et al. proposed speed-independent RCA with carry completion signal [18]. In 1960s that circuit was carefully analyzed and improved [19-21]. In 1980 Seitz used RCA for illustrating his concept of equipotential region and his approach to self-timed system design [4]. Now we use RCA as a CL for illustrating our approach to SIM design. As it was shown in Section 4.2 the turn-on and turn-off delays of the OVD circuit are proportional to the equivalent capacitance Ceq associated with OVD circuit input. Capacitance Ceq depends linearly on a number of gates N in CMOS CL. To speed up a SIM it is necessary to reduce a number N. This can be reached by structural decomposition CMOS CL into subcircuits CL1, CL2, etc. Each subcircuit CLi is connected to its own detecting circuit OVDi or directly to the power supply if this subcircuit transition does not affect the transition duration in CL as a whole. Each detecting circuit OVDi generates its own OV signal which is combined with other OVDs' output signals via a multi-input OR (NOR) element. The output signal of that element serves as OV signal of the CMOS CL. Multi-bit RCA computation time is determined by length of maximal activated carry chain. A lot of papers were devoted to analysis of carry generation and carry propagation in RCA [19-21], many of them contained their own methods for estimation or calculation of average maximal activated carry chain. We do not intend to add another one. Let us have a look inside RCA. As it was mentioned above RCA consists of one-bit full adders and each full adder consists of two parts: forming sum si part and forming carry ci+1 part (Fig.16). In multi-bit RCA all forming sum parts do not interact with each other and do not affect on transition duration in RCA. Each forming carry ci+1 part receives ci signal from preceding forming carry part and sends ci+1 signal to consequent one. To decompose RCA we use three heuristic tricks: (i) All forming sum parts we connect directly to power supply. (ii) We divide each forming carry part into three subcircuits denoted in Fig.16 by numbers 1,2 and 3. All subcircuits 1 we connect скачать реферат 1 2 3 4 5 Не нашли нужную работу? Закажи реферат, курсовую, диплом на заказ Внимание! Студенческий отдых и мегатусовка после сессии!
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