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реферат на тему: Physical Methods of Speed-Independent Module Design

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NMOS transistors (Fig.12). The scheme for n-bit bus control contains n line transition detectors (LTDs) and n AND-gates. Outputs of AND-gates are united in node M forming wired OR. The output inverter serves as a pulse shaper. Capacitors C1 and C2 are intended to prolong rise time of the LTD output signal (true and complementary). This is necessary for reliable detection.

The main drawback of the circuit is speed dependence. One can see that if true and complementary address bit signal have different propagation delays, the conducting path via NMOS transistors will never be formed. Using the OVD circuit proposed in Section 4.2 as LTD we can avoid this drawback. Note that address transmission through the address bus is unidirectional. So to detect completion of bus transition it is enough to recognize the bus state at the destination end. For this purpose we modify CL to consist of n lines. The modification means introducing n LTDs, each actually a CMOS inverter chain. Each chain contains two inverters loaded with a capacitance (Fig.13). Input of each LTD is connected with corresponding line of the bus at the destination end. Power supply pads of all LTDs are connected to the current input of the same OVD circuit.

The parameters of the input current signal for the OVD circuit are varied by (i) value of capacitances C1 and C2 ; (ii) dimensions of MOS transistors M1 -M4 . Since all transitions in CL are of the same duration and can be lengthened to be outlast the OVD turning-on time, we simplify the interface circuitry by disallowing the asymmetrical delay. Due to short duration of normal transition in this CL we must take into account the integral nature of the sensitivity of the OVD circuit. OVD sensitivity depends on both amplitude and width of input current pulse. Simulated operation region of the OVD circuit for current pulses shorter than 30ns is shown in Fig.14. It is obvious that in this case the threshold of the OVD circuit must be determined by threshold charge Qth value. The OVD input charge Q equals to where I is OVD input current, t is a moment of time when transition occurs, w is a width of input current pulse. Turning-on condition for the OVD circuit is Q=Qth.

When the LTD circuit shown in Fig.13 is used, the charge value Q is determined by either C1 or C2. Namely, if the line goes from low to high voltage, Q=VC2. If the line goes in the reverse direction then where V is charging/discharging voltage, approximately equal to the effective power supply voltage: VVdd -V. Here Vdd is OVD power supply voltage and V is CVC voltage drop. The OVD circuit with typical parameters (See Table 1) has a threshold charge value Qth =4.010-12 C. When C1 =C2 =CL , the minimal value of CL providing OVD capacity for operation is about 1.010-12 F. Influence of transistors M1 -M4 dimensions on LTD delay d is determined by approximation [17]:

where ~ is a sign of proportionality, Gn and Gp are the conductances of NMOS and PMOS transistors respectively (CL =C1 =C2.) Since and where W and L are width and length of transistor channels of the corresponding conduction type, the LTD delay d is proportional to . It has been obtained that for , , CL=1.0pF and Vdd-V=5.0V the LTD delay d=7.6ns. When LTD works jointly with the OVD in the speed-independent bus, the real value of the LTD delay will increase by 30-40 percent due to OVD's R1 effect on the effective power supply voltage. To determine
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the appropriate value of R1 in the OVD circuit we must know threshold input current Ith corresponding to threshold voltage drop Vth recommended to be equal to 400mV. Average input current Iav in transient state of one line is determined by the expression Iav =CLv where v is the average rate of increase in the output signal for an inverter included in LTD. For typical values v=1.0109 Volts per second and CL =1.0pF, Iav =1.0mA. Accepting Ith =0.4mA and Imax=2.0mA we obtain R1=1k and rb=100. Simulation has shown that in this case OVD turning-on delay can be approximated by an empirical expression: ton[ns]=8.1+0.1n where n is the address bus bit capacity. Total delay of recognizing address transition ttot =dg+ton where g is a coefficient of the LTD delay increase due to reducing power supply voltage. As we showed above g1.35. It can be seen that if n=32, ttot=21.6ns.

4.4 Speed-independent adder

The circuit we use in this Section as a CL was a touch-stone for many speed-independent circuit designers for about four decades. We mean a ripple carry adder (RCA) which is actually a chain of one-bit full adders (Fig.14).

Each full adder calculates two Boolean functions: sum si=aibici and output carry ci+1=aibi+bici+aici where ai, bi are summands, ci is input carry and stands for XOR operation. In 1955 Gilchrist et al. proposed speed-independent RCA with carry completion signal [18]. In 1960s that circuit was carefully analyzed and improved [19-21]. In 1980 Seitz used RCA for illustrating his concept of equipotential region and his approach to self-timed system design [4]. Now we use RCA as a CL for illustrating our approach to SIM design. As it was shown in Section 4.2 the turn-on and turn-off delays of the OVD circuit are proportional to the equivalent capacitance Ceq associated with OVD circuit input. Capacitance Ceq depends linearly on a number of gates N in CMOS CL. To speed up a SIM it is necessary to reduce a number N. This can be reached by structural decomposition CMOS CL into subcircuits CL1, CL2, etc. Each subcircuit CLi is connected to its own detecting circuit OVDi or directly to the power supply if this subcircuit transition does not affect the transition duration in CL as a whole. Each detecting circuit OVDi generates its own OV signal which is combined with other OVDs' output signals via a multi-input OR (NOR) element. The output signal of that element serves as OV signal of the CMOS CL. Multi-bit RCA computation time is determined by length of maximal activated carry chain. A lot of papers were devoted to analysis of carry generation and carry propagation in RCA [19-21], many of them contained their own methods for estimation or calculation of average maximal activated carry chain. We do not intend to add another one. Let us have a look inside RCA. As it was mentioned above RCA consists of one-bit full adders and each full adder consists of two parts: forming sum si part and forming carry ci+1 part (Fig.16). In multi-bit RCA all forming sum parts do not interact with each other and do not affect on transition duration in RCA. Each forming carry ci+1 part receives ci signal from preceding forming carry part and sends ci+1 signal to consequent one. To decompose RCA we use three heuristic tricks: (i) All forming sum parts we connect directly to power supply. (ii) We divide each forming carry part into three subcircuits denoted in Fig.16 by numbers 1,2 and 3. All subcircuits 1 we connect

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